(1) Field of the Invention
The invention relates to a method of forming an inductor in the fabrication of integrated circuits, and more particularly, to a method of forming a high quality inductor using bonding techniques in the manufacture of integrated circuits.
(2) Description of the Prior Art
Increasing demands for wireless communications motivate a growing interest in low-cost, compact monolithic personal communication transceivers. High performance radio frequency (RF) inductors are the key components for implementing critical building blocks such as low-noise RF voltage-controlled oscillators (VCOs), low-loss impedance matching networks, passive filters, low-noise amplifiers and inductive loads for power amplifiers, etc. Critical parameters include inductance value, quality factor, and self-resonant frequency. However, the difficulty of realizing high quality factor (Q) inductors remains a challenge especially on silicon radio frequency (RF) integrated circuit (IC) applications. Conventional inductors built on silicon have strictly planar structures and using conventional fabrication processes suffers from several limitations. Most structures and methods currently used for fabricating high Q inductors are in hybrid circuits, monolithic microwave integrated circuits (MMICs), or discrete applications which are not readily compatible with silicon VLSI processing. Consequently, the ability of integrating high quality factor (high Q) inductors on active silicon is limited.
In the past, many fabricating techniques, methods, and processes were proposed to improve the performance of the integrated conductor. In fact, most of these techniques are not cost effective or practical, requiring process changes such as depositing thicker metal/dielectric layers or starting with high resistivity substrates. Expensive processes such as the selective removal of the silicon substrate underneath the inductors has been introduced to eliminate the substrate parasitic effects. However, this processing technique raises reliability issues like packaging yield and long-term mechanical stability. Also, the typical aluminum-copper (AlCu) interconnects which are found in the conventional silicon process have higher resistivity than gold (Au) metallization used in GaAs technology. This is a concern for obtaining high inductance (L) value. Another approach is to make an active inductive component which simulates the electrical properties of an inductor by active circuitry. It is possible to achieve very high Q-factor and inductance in a relatively small size this way. However, this approach may suffer from high power consumption and high noise levels that are not acceptable for high frequency applications.
Most of these complex processes used seem promising, but they are uncommon to most semiconductor processes and they will result in high production costs. Currently, the conventional spiral inductor is still the most commonly used. This spiral inductor which is built horizontally on the substrate surface not only occupies large chip area, but also suffers from low Q-factor and high parasitic effects due to substrate losses.
A number of papers have discussed the use of inductors for new device technologies such as RF devices. The first two references listed provide more general discussions of inductors while the remaining papers discuss spiral inductors. Refer to: (1) “New Development Trends for Silicon RF Device Technologies,” by N. Camilleri et. al, IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium, p. 5-8, 1994; (2) “Future Directions in Silicon IC's for RF Personal Communications,” by P. R. Gray et al, Proc. Custom Integrated Circuits Conference, p. 83-89, 1995; (3) “High Q CMOS-Compatible Microwave Inductors Using Double-Metal Interconnection Silicon Technology,” IEEE Microwave and Guided Wave Letters, Vol. 7, No. 2, p. 45-47, February 1997; (4) “RF Circuit Design Aspects of Spiral Inductors on Silicon,” by J. N. Burghartz et al, IEEE Journal of Solid-State Circuits, Vol. 33, No. 12, p. 246-247, December 1998; (5) “Novel Substrate Contact Structure for High-Q Silicon Integrated Spiral Inductors,” by J. N. Burghartz et al, Tech. Dig. Int. Electron Devices Meeting, p. 55-58, 1997; (6) “Microwave Inductors and Capacitors in Standard Multilevel Interconnect Silicon Technology,” by J. N. Burghartz et al, IEEE Transactions on Microwave Theory and Techniques, Vol. 44, No. 1, P. 100-104, January 1996; (7) “The Modeling, Characterization and Design of Monolithic Inductors for Silicon RF IC's”, by J. R. Long et al, IEEE Journal of Solid-State Circuits, Vol. 32, No. 3, p. 357-368, March 1997; (8) “Multilevel Spiral Inductors Using VLSI Interconnect Technology,” by J. N. Burghartz et al, IEEE Electron Device Letters, Vol. 17, No. 9, p. 428-430, September 1996; (9) “Si IC-Compatible Inductors and LC Passive Filters,” by N. M. Nguyen et al, IEEE Journal of Solid-State Circuits, Vol. 25, No. 4, p. 1028-1031, August 1990; (10) “Experimental Study on Spiral Inductors,” by S. Chaki et al, IEEE Microwave Symp. Dig. MTT-S, p. 753-756, 1995.
U.S. Pat. No. 5,886,393 to Merrill et al teaches forming an inductor in a package form using bonding wire segments. The inductor can have any shape. U.S. Pat. No. 5,963,110 to Ihara et al shows an inductor formed on a ceramic substrate using bonding wire divided into sections and having daisy-chained connections across landing pads. U.S. Pat. No. 5,905,418 to Ehara et al, U.S. Pat. No. 5,945,880 to Souetinov and U.S. Pat. No. 5,640,127 to Metz disclose inductors formed in whole or in part of bonding wire.